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87c196kr, 87c196jv, 87c196jt, 87c196jr, and 87C196CA advanced 16-bit chmos microcontrollers automotive datasheet product features n C40c to +125c ambient n high performance chmos 16-bit cpu n up to 48 kbytes of on-chip eprom n up to 1.5 kbytes of on-chip register ram n up to 512 bytes of additional ram (code ram) n register-register architecture n up to eight channel/10-bit a/d with sample/hold n up to 37 prioritized interrupt sources n up to seven 8-bit (56) i/o ports n full duplex serial i/o port n dedicated baud rate generator n interprocessor communication slave port n high speed peripheral transaction server (pts) n two 16-bit software timers n up to 10 high speed capture/compare (epa) n full duplex synchronous serial i/o port (ssio) n two flexible 16-bit timer/counters n quadrature counting inputs n flexible 8-/16-bit external bus n programmable bus (hld/hlda) n 1.75 s 16 x 16 multiply n 3 s 32/16 divide n 68-pin and 52-pin plcc packages n supports can (controller area network) specification 2.0 (ca only) order number: 270827-007 april 1998
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 87c196kr, jv, jt, jr and ca microcontrollers may contain design defects or errors known as errata which may cause the produ ct to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1998 *third-party brands and names are the property of their respective owners.
datasheet 3 automotive 87c196kr, jv, jt, jr, and ca microcontrollers contents 1.0 introduction .................................................................................................................. 5 2.0 architecture .................................................................................................................. 6 2.1 cpu features........................................................................................................ 6 2.2 peripheral features...............................................................................................6 2.3 new instructions.................................................................................................... 7 2.3.1 xch/xchb ............................................................................................... 7 2.3.2 bmovi ...................................................................................................... 7 2.3.3 tijmp ....................................................................................................... 7 2.3.4 epts/dpts ............................................................................................. 7 2.4 sfr operation ...................................................................................................... 7 3.0 packaging information ............................................................................................. 9 4.0 electrical characteristics ...................................................................................... 14 4.1 absolute maximum ratings................................................................................. 14 4.2 operating conditions........................................................................................... 14 4.3 dc characteristics .............................................................................................. 15 4.4 ac characteristics............................................................................................... 18 4.4.1 explanation of ac symbols....................................................................23 4.4.2 eprom specifications ........................................................................... 23 4.4.3 a to d converter specifications ............................................................. 25 4.4.4 ac characteristicsslave port ............................................................. 28 4.4.5 ac characteristicsserial port shift register mode ......................... 30 4.4.6 waveformserial portshift register mode 0 ....................................30 5.0 52-lead devices ....................................................................................................... 31 6.0 design considerations .......................................................................................... 32 6.1 87c196kr, jv, jt, jr, and ca design considerations .....................................32 6.2 87c196jr c-step to jr d-step C or C jv/jt a-step design considerations .................................................................................................... 33 6.2.1 87C196CA design considerations.........................................................36 7.0 revision history ....................................................................................................... 37
87c196kr, jv, jt, jr, and ca microcontrollers automotive 4 datasheet figures 1 block diagram....................................................................................................... 8 2 8xc196kx, jx, and ca family nomenclature ...................................................... 8 3 87c196kr 68-pin plcc package diagram ......................................................... 9 4 87c196jv, jt, jr 52-pin plcc package diagram ........................................... 10 5 87C196CA 68-pin plcc package diagram ....................................................... 11 6 87c196kr and jr i cc vs. frequency................................................................. 16 7jt i cc vs. frequency .......................................................................................... 17 8 87C196CA i cc vs. frequency ............................................................................. 17 9 system bus timing ............................................................................................. 20 10 ready/buswidth timing .................................................................................... 21 11 external clock drive waveforms ........................................................................ 21 12 ac testing input, output waveforms ................................................................. 22 13 float waveforms ................................................................................................. 22 14 slave programming mode data program mode with single program pulse .................................................................................................... 24 15 slave programming mode in word dump or data verify mode with auto increment .................................................................................................... 24 16 slave programming mode timing in data program mode with repeated prog pulse and auto increment....................................................... 25 17 hold timings..................................................................................................... 27 18 slave port waveform (slpl = 0) ........................................................................ 28 19 slave port waveform (slpl = 1) ........................................................................ 29 20 serial port waveformshift register mode ....................................................... 30 tables 1 87c196kx and jx features summary .................................................................. 6 1 pin descriptions .................................................................................................. 12 2 absolute maximum ratings ................................................................................ 14 3 operating conditions .......................................................................................... 14 4 dc characteristics .............................................................................................. 15 5 ac characteristics .............................................................................................. 18 6 external clock drive............................................................................................ 21 7 thermal characteristics ...................................................................................... 22 8 ac eprom programming characteristics.......................................................... 23 9 dc eprom programming characteristics ......................................................... 24 10 a/d operating conditions ................................................................................... 25 11 a/d operating parameter values........................................................................ 26 12 hold#/hlda# timings ...................................................................................... 27 13 dc specifications in hold ................................................................................. 27 14 slave port timingC(slpl = 0)............................................................................. 28 15 slave port timingC(slpl = 1)............................................................................. 29 16 serial port timingshift register mode ............................................................ 30
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 5 1.0 introduction the mcs 96 microcontroller family members are all high performance microcontrollers with a 16- bit cpu. the 87c196kx and jx family members are composed of the high-speed (16 mhz) core as well as the following peripherals: ? up to 48 kbytes of programmable eprom ? up to 1.5 kbytes of register ram and 512 bytes of code ram (16-bit addressing modes) with the ability to execute from this ram space ? up to eight channelsC10-bit/ 3 lsb analog to digital converter with programmable s/h times with conversion times < 5 s at 16 mhz ? an asynchronous/synchronous serial i/o port (8096 compatible) with a dedicated 16-bit baud rate generator ? interprocessor communication slave port ? synchronous serial i/o port with full duplex master/slave transceivers ? a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities ? up to ten modularized multiplexed high speed i/o for capture and compare (called event processor array) with 250 ns resolution and double buffered inputs ? a sophisticated prioritized interrupt structure with programmable peripheral transaction server (pts). the pts has several channel modes, including single/burst block transfers from any memory location to any memory location, a pwm and pwm toggle mode to be used in conjunction with the epa, and an a/d scan mode. ? serial communications protocol can 2.0 with 15 message objects of 8 bytes data length (ca only) the 87c196kr, jv, jt, jr, and ca devices represent the fourth generation of mcs ? 96 microcontroller products implemented on intel's advanced 1 micron process technology. these products are based on the 80c196kb device with improvements for automotive applications. the instruction set is a true super set of 80c196kb. the 87c196jr, jt, and jv are 52-pin versions of the 87c196kr device. the 87c196jv and jt devices are memory scalars of the 87c196jr and are designed for strict functional and electrical compatibility. the jt has 32 kbytes of on-chip eprom, 1.0 kbytes of register ram and 512 bytes of code ram. the jv has 48 kbytes of on-chip eprom, 1.5 kbytes of register ram and 512 bytes of code ram. the 87C196CA device is a memory scalar of the 87c196kr in a 68-pin package with 32 kbytes of on-chip eprom, 1.0 kbytes of register ram, and 256 bytes of code ram. in addition, the ca contains an extra peripheral for serial communications protocol can 2.0. table 1 summarizes the features of the 87c196kx, jx, and ca devices.
87c196kr, jv, jt, jr, ca microcontrollers automotive 6 datasheet refer to the following datasheets for higher frequency versions of devices contained within this datasheet: ? 87c196jt 20 mhz advanced 16-bit chmos microcontroller datasheet, order #272529 ? 87c196jv 20 mhz advanced 16-bit chmos microcontroller datasheet, order #272580. 2.0 architecture the 87c196kr, jv, jt, jr, and ca are members of the mcs 96 microcontroller family, have the same architecture and use the same instruction set as the 80c196kb/kc. many new features have been added including: 2.1 cpu features ? powerdown and idle modes ? 16 mhz operating frequency ? a high performance peripheral transaction server (pts) ? up to 37 interrupt vectors ? up to 512 bytes of code ram ? up to 1.5 kbytes of register ram ? windowing allows 8-bit addressing to some 16-bit addresses ? 1.75 s 16 x 16 multiply ? 3 s 32/16 divide ? oscillator fail detect 2.2 peripheral features ? programmable a/d conversion and s/h times ? up to 10 capture/compare i/o with 2 flexible timers ? synchronous serial i/o port for full duplex serial i/o table 1. 87c196kx and jx features summary device pins/package eprom reg ram code ram i/o epa sio ssio a/d 87c196kr 68-pin plcc 16 k 512 256 56 10 y y 8 87c196jv 52-pin plcc 48 k 1.5 k 512 41 6 y y 6 87c196jt 52-pin plcc 32 k 1.0 k 512 41 6 y y 6 87c196jr 52-pin plcc 16 k 512 256 41 6 y y 6 87C196CA 68-pin plcc 32 k 1.0 k 256 38 6 y y 6
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 7 ? total utilization of all available pins (i/o mux'd with control) ? two 16-bit timers with prescale, cascading and quadrature counting capabilities ? up to 12 externally triggered interrupts 2.3 new instructions 2.3.1 xch/xchb exchange the contents of two locations, either word or byte is supported. 2.3.2 bmovi interruptable block move instruction, allows the user to be interrupted during long executing block moves. 2.3.3 tijmp table indirect jump. this instruction incorporates a way to do complex case level branches through one instruction. an example of such code savings: several interrupt sources and only one interrupt vector. the tijmp instruction will sort through the sources and branch to the appropriate sub-code level in one instruction. this instruction was added especially for the epa structure, but has other code saving advantages. 2.3.4 epts/dpts enable and disable pts interrupts (works like ei and di). 2.4 sfr operation an additional 256 bytes of sfr registers were added to the 8xc196kx, jx, and ca devices. these locations were added to support the wide range of on-chip peripherals that these devices have. this memory space (1f00C1fffh) has the ability to be addressed as direct 8-bit addresses through the windowing technique. any 32-, 64- or 128-byte section can be relocated in the upper 32, 64 or 128 bytes of the internal register ram (080Cffh) address space. the ca contains an additional 256 bytes of sfr registers for can functions located in memory space ie00-1effh.
87c196kr, jv, jt, jr, ca microcontrollers automotive 8 datasheet figure 1. block diagram figure 2. 8xc196kx, jx, and ca family nomenclature a4643-01 clock generator port0 epa0 - 9 ach0 - 7 port1 t2clk t2dir t1clk t1dir port2 port3 port4 port5 sc0 sc1 sd0 sd1 txd rxd port6 i/o ports timer 1 & 2 register ram a/d converter (10-bit) [8 channels] peripheral transaction server (pts) power and gnd alu xtal2 control signals addr/ data bus xtal1 16 code ram on-chip eprom (optional) event processor array (epa) programmable interrupt controller serial i/o (uart & ssio) v cc v ss v ss v ss v ref angnd 16 memory controller with prefetch queue a4644-02 an 87 c r k 196 0 = romless 3 = masked rom 7 = eprom, otp, qrom product designation: kr, jv, jt, jr, ca frequency designation (no mark = 16 mhz) product family chmos technology program memory options: n = plcc (plastic leaded chip carrier) package type options: a = -40 ? c to +125 ? c ambient with intel standard burn-in temperature and burn-in options:
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 9 3.0 packaging information figure 3. 87c196kr 68-pin plcc package diagram a4645-02 p6.2 / t1clk p6.1 / epa9 p6.0 / epa8 p1.0 / epa0 / t2clk p1.1 / epa1 p1.2 / epa2 / t2dir p1.3 / epa3 p1.4 / epa4 p1.5 / epa5 p1.6 / epa6 p1.7 / epa7 v ref angnd p0.7 / ach7 p0.6 / ach6 p0.5 / ach5 p0.4 / ach4 wr# / wrl# / p5.2 bhe# / wrh# / p5.5 rd# / p5.3 v pp v ss ale / adv# / p5.0 inst / p5.1 ready / p5.6 p5.4 / slpint v ss xtal1 xtal2 p6.7 / sd1 p6.6 / sc1 p6.5 / sd0 p6.4 / sc0 p6.3 / t1dir buswidth / p5.7 ad15 / p4.7 ad14 / p4.6 ad13 / p4.5 ad12 / p4.4 ad11 / p4.3 ad10 / p4.2 ad9 / p4.1 ad8 / p4.0 ad7 / p3.7 ad6 / p3.6 ad5 / p3.5 ad4 / p3.4 ad3 / p3.3 ad2 / p3.2 ad1 / p3.1 ad0 / p3.0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 87c196kr 68-pin plcc view of component as mounted on pc board 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 reset# nmi ea# v ss v cc p2.0 / txd p2.1 / rxd p2.2 / extint p2.3 / breq# p2.4 / intout# p2.5 / hld# p2.6 / hlda# p2.7 / clkout p0.0 / ach0 p0.1 / ach1 p0.2 / ach2 p0.3 / ach3 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
87c196kr, jv, jt, jr, ca microcontrollers automotive 10 datasheet figure 4. 87c196jv, jt, jr 52-pin plcc package diagram a4646-02 p6.1 / epa9 p6.0 / epa8 p1.0 / epa0 p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 v ref angnd p0.7 / ach7 p0.6 / ach6 p0.5 / ach5 p0.4 / ach4 p0.3 / ach3 ad15 / p4.7 wr# / wrl# / p5.2 rd# / p5.3 v pp v ss ale / adv# / p5.0 v ss xtal1 xtal2 p6.7 / sd1 p6.6 / sc1 p6.5 / sd0 p6.4 / sc0 ad14 / p4.6 ad13 / p4.5 ad12 / p4.4 ad11 / p4.3 ad10 / p4.2 ad9 / p4.1 ad8 / p4.0 ad7 / p3.7 ad6 / p3.6 ad5 / p3.5 ad4 / p3.4 ad3 / p3.3 ad2 / p3.2 46 45 44 43 42 41 40 39 38 37 36 35 34 87c196jv 87c196jt 87c196jr 52-pin plcc view of component as mounted on pc board 8 9 10 11 12 13 14 15 16 17 18 19 20 ad1 / p3.1 ad0 / p3.0 reset# ea# v ss v cc p2.0 / txd p2.1 / rxd p2.2 / extint p2.4 p2.6 p2.7 / clkout p0.2 / ach2 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 1 52 51 50 49 48 47
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 11 figure 5. 87C196CA 68-pin plcc package diagram a4676-01 nc nc v cc epa9 / p6.1 epa8 / p6.0 epa0 / p1.0 / t2clk epa1 / p1.1 epa2 / p1.2 / t2dir epa3 / p1.3 nc v ref angnd ach7 / p0.7 ach6 / p0.6 ach5 / p0.5 ach4 / p0.4 nc wr# / p5.2 wrh# / p5.5 rd# / p5.3 v pp v ss ale / p5.0 ready / p5.6 p5.4 v ss1 xtal1 xtal2 rxcan txcan sd1 / p6.7 sc1 / p6.6 sd0 / p6.5 sc0 / p6.4 nc ad15 / p4.7 ad14 / p4.6 ad13 / p4.5 ad12 / p4.4 ad11 / p4.3 ad10 / p4.2 ad9 / p4.1 ad8 / p4.0 ad7 / p3.7 ad6 / p3.6 ad5 / p3.5 ad4 / p3.4 ad3 / p3.3 ad2 / p3.2 nc nc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 87C196CA 68 C ld plcc view of component as mounted on pc board 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p3.1 / ad1 p3.0 / ad0 reset# nmi ea# v ss1 v cc v ss txd / p2.0 rxd / p2.1 extint / p2.2 p2.4 p2.6 clkout / p2.7 ach2 / p0.2 ach3 / p0.3 nc 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
87c196kr, jv, jt, jr, ca microcontrollers automotive 12 datasheet table 2. pin descriptions (sheet 1 of 2) symbol name and function v cc main supply voltage (+5 v). v ss digital circuit ground (0 v). there are three v ss pins, all of which must be connected to a single ground plane. v ref reference for the a/d converter (+5 v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. v pp programming voltage for the eprom parts. it should be +12.5 v for programming. it is also the timing pin for the return from powerdown circuit. connect this pin with a 1 f capacitor to v ss and a 1 m w resistor to v cc . if this function is not used, v pp may be tied to v cc . angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . xtal1 input of the oscillator inverter and the internal clock generator. xtal2 output of the oscillator inverter. p2.7/clkout output of the internal clock generator. the frequency is ? the oscillator frequency. it has a 50% duty cycle. also lsio pin when not used as clkout. reset# reset input to the chip. input low for at least 16 state times will reset the chip. the subsequent low to high transition resynchronizes clkout and commences a 10- state time sequence in which the psw is cleared, bytes are read from 2018h and 201ah loading the ccbs, and a jump to location 2080h is executed. input high for normal operation. reset# has an internal pullup. p5.7/buswidth input for bus width selection. if ccr bit 1 is a one and ccr1 bit 2 is a one, this pin dynamically controls the bus width of the bus cycle in progress. if buswidth is low, an 8-bit cycle occurs. if buswidth is high, a 16-bit cycle occurs. if ccr bit 1 is 0 and ccr1 bit 2 is 1, all bus cycles are 8-bit; if ccr bit 1 is 1 and ccr1 bit 2 is 0, all bus cycles are 16-bit. ccr bit 1 =0'' and ccr1 bit 2 = 0 is illegal. also an lsio pin when not used as buswidth. nmi a positive transition causes a non-maskable interrupt vector through memory location 203eh. p5.1/inst output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is active only during external memory fetches. during internal [ep]rom fetches inst is held low. also lsio when not inst. ea# input for memory select (external access). ea# equal to a high causes memory accesses within the [ep]rom address space to be directed to on-chip eprom/ rom. ea# equal to a low causes accesses to these locations to be directed to off- chip memory. ea# = +12.5 v causes execution to begin in the programming mode. ea# latched at reset. p5.0/ale/adv# address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when the pin is adv#, it goes inactive (high) at the end of the bus cycle. adv# can be used as a chip select for external memory. ale/adv# is active only during external memory accesses. also lsio when not used as ale. p5.3/rd# read signal output to external memory. rd# is active only during external memory reads. lsio when not used as rd#. p5.2/wr#/wrl# write and write low output to external memory, as selected by the ccr, wr# will go low for every external write, while wrl# will go low only for external writes where an even byte is being written. wr#/wrl# is active during external memory writes. also an lsio pin when not used as wr#/wrl#.
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 13 p5.5/bhe#/wrh# byte high enable or write high output, as selected by the ccr. bhe# = 0 selects the bank of memory that is connected to the high byte of the data bus. a0 = 0 selects that bank of memory that is connected to the low byte. thus accesses to a 16-bit wide memory can be to the low byte only (a0 = 0, bhe# =1), to the high byte only (a0 = 1, bhe# = 0) or both bytes (a0 = 0, bhe# = 0). if the wrh# function is selected, the pin will go low if the bus cycle is writing to an odd memory location. bhe#/wrh# is only valid during 16-bit external memory write cycles. also an lsio pin when not bhe#/wrh#. p5.6/ready ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. if the pin is high, cpu operation continues in a normal manner. if the pin is low prior to the falling edge of clkout, the memory controller goes into a wait state mode until the next positive transition in clkout occurs with ready high. when external memory is not used, ready has no effect. the max number of wait states inserted into the bus cycle is controlled by the ccr/ccr1. also an lsio pin when ready is not selected. p5.4/slpint dual functional i/o pin. as a bidirectional port pin (lsio) or as a system function. the system function is a slave port interrupt output pin. p6.2/t1clk dual function i/o pin. primary function is that of a bidirectional i/o pin (lsio); however it may also be used as a timer1 clock input. the timer1 will increment or decrement on both positive and negative edges of this pin. p6.3/t1dir dual function i/o pin. primary function is that of a bidirectional i/o pin (lsio); however it may also be used as a timer1 direction input. the timer1 will increment when this pin is high and decrements when this pin is low. port1/epa0C7 p6.0C6.1/epa8C9 dual function i/o port pins. primary function is that of bidirectional i/o (lsio). system function is that of high speed capture and compare. epa0 and epa2 have yet another function of t2clk and t2dir of the timer2 timer/counter. port 0/ach0C7 8-bit high impedance input-only port. these pins can be used as digital inputs and/ or as analog inputs to the on-chip a/d converter. these pins are also used as inputs to eprom parts to select the programming mode. p6.4C6.7/ssio dual function i/o ports that have a system function as synchronous serial i/o. two pins are clocks and two pins are data, providing full duplex capability. port 2 8-bit multi-functional port. all of its pins are shared with other functions. port 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. txcan push-pull output to the can bus line. rxcan high-impedance input-only from the can bus line. table 2. pin descriptions (sheet 2 of 2) symbol name and function
87c196kr, jv, jt, jr, ca microcontrollers automotive 14 datasheet 4.0 electrical characteristics note: this document contains information on products in production. the specifications are subject to change without notice. 4.1 absolute maximum ratings warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. 4.2 operating conditions warning: operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 3. absolute maximum ratings parameter maximum rating storage temperature C60c to +150c voltage from v pp or ea# to v ss or angnd C0.5 v to +13.0 v voltage from any other pin to v ss or angnd C0.5 v to +7.0 v power dissipation 0.5 w table 4. operating conditions parameter values t a (ambient temperature under bias) C40c to +125c v cc (digital supply voltage) 4.50 v to 5.50 v v ref (analog supply voltage) (notes 1, 2) 4.50 v to 5.50 v f osc (oscillator frequency): 4 mhz to 16 mhz (2) note: 1. angnd and v ss should be nominally at the same potential. 2. device is static and should operate below 1 hz, but only tested down to 4 mhz.
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 15 4.3 dc characteristics table 5. dc characteristics (sheet 1 of 2) symbol parameter min typical max units test conditions i cc v cc supply current (C40c to +125c ambient) 50 75 (jv=80) (ca=90) ma x tal1 = 16 mhz, v cc = v pp = v ref = 5.5 v (while device is in reset) i cc1 active mode supply current (typical) 50 (jv=55) ma i ref a/d reference supply current 25ma i idle idle mode current 15 30 (jv=32) (ca=40) ma x tal 1 = 16 mhz, v cc = v pp = v ref = 5.5 v i pd powerdown mode current 50 a v cc = v pp = v ref = 5.5 v (note 4) v il input low voltage (all pins) C0.5 v 0.3 v cc v v ih input high voltage (all pins) 0.7 v cc v cc + 0.5 v (note 5) v ol output low voltage (outputs configured as push/pull) 0.3 0.45 1.5 v i ol = 200 a (note 3) i ol = 3.2 ma i ol = 7.0 ma v oh output high voltage (outputs configured as complementary) v cc C 0.3 v cc C 0.7 v cc C 1.5 v i oh = C 200 a (note 3) i oh = C 3.2 ma i oh = C 7.0 ma i li input leakage current (standard inputs) 8 jt,jv,ca: 10 a v ss v in v cc (note 2) i li1 input leakage current (port 0a/d inputs) 1 jt,jv: 2 ca: 1.5 a v ss v in v cc i ih input high current (nmi pin) +175 a v ss v in v cc v oh1 slpint (p5.4) and hlda (p2.6) output high voltage in reset 2.0 v i oh = 0.8 ma (note 8) v oh2 output high voltage in reset v cc C 1 v v i oh = C 15 a (notes 1, 6) notes: 1. all bd (bidirectional) pins except p5.5/inst and p2.7/clkout which are excluded due to their not being weakly pulled high in reset. bd pins include port1, port 2, port3, port4, port5, and port6. 2. standard input pins include xtal1, ea#, reset#, and ports 1,2,3,4,5,6 when configured as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5.0 v. 5. v ih max for port0 is v ref + 0.5 v. 6. refer to voh2/ioh2 specification errata #1 in errata section of this datasheet. 7. this specification is not tested in production and is based upon theoretical estimates and/or product characterization. 8. violating these specifications in reset may cause the device to enter test modes (p5.4 and p2.6).
87c196kr, jv, jt, jr, ca microcontrollers automotive 16 datasheet i oh2 (kr) output high current in reset C6 C15 C20 C35 C60 C70 a v oh2 = v cc C 1.0 v v oh2 = v cc C 2.5 v v oh2 = v cc C 4.0 v i oh2 (jv, jt, jr,ca) output high current in reset C30 C75 C90 C120 C240 C280 a v oh2 = v cc C 1.0 v v oh2 = v cc C 2.5 v v oh2 = v cc C 4.0 v r rst reset pullup resistor 6 k 65 k w v ol3 output low voltage in reset (reset pin only) 0.3 0.5 0.8 v i ol3 = 4 ma (note 7) i ol3 = 6 ma i ol3 = 10 ma c s pin capacitance (any pin to v ss ) 10 pf f test = 1.0 mhz r wpu weak pullup resistance (approx.) 150 k w (note 4) figure 6. 87c196kr and jr i cc vs. frequency table 5. dc characteristics (sheet 2 of 2) symbol parameter min typical max units test conditions notes: 1. all bd (bidirectional) pins except p5.5/inst and p2.7/clkout which are excluded due to their not being weakly pulled high in reset. bd pins include port1, port 2, port3, port4, port5, and port6. 2. standard input pins include xtal1, ea#, reset#, and ports 1,2,3,4,5,6 when configured as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5.0 v. 5. v ih max for port0 is v ref + 0.5 v. 6. refer to voh2/ioh2 specification errata #1 in errata section of this datasheet. 7. this specification is not tested in production and is based upon theoretical estimates and/or product characterization. 8. violating these specifications in reset may cause the device to enter test modes (p5.4 and p2.6). a4647-02 i cc max i cc typical i idle max i idle typical 80 70 60 50 40 30 20 10 0 4 mhz 10 mhz 15 mhz i cc = [ma] kr/jr i cc vs. frequency notes: i idle max = 1.65 x freq + 2.2 i cc max = 3.88 x freq + 13.43
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 17 figure 7. jt i cc vs. frequency figure 8. 87C196CA i cc vs. frequency a5877-01 0 0 4 mhz 10 mhz 20 mhz 20 30 40 10 50 60 70 note: 90 i cc vs frequency i cc max i cc (ma) i idle max i idle max = 1.25 x freq + 15 i cc max = 3.25 x freq + 23 a5862-01 90 80 70 60 50 40 30 20 10 0 2 8 14 20 active i cc max = 90 ma active i cc = 75 ma idle max = 40 ma idle i cc = 32 ma i cc (ma)
87c196kr, jv, jt, jr, ca microcontrollers automotive 18 datasheet 4.4 ac characteristics table 6. ac characteristics (sheet 1 of 2) (over specified operating conditions); test conditions: capacitance load on all pins = 100 pf, rise and fall times = 10 ns, f osc =16mhz symbol parameter min max units the system must meet these specifications to work with the 87c196kr, jv, jt, jr, ca microcontroller. t avyv address valid to ready setup 2 t osc C75 ns t llyv ale low to ready setup t osc C70 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc C30 ns (1) t llyx ready hold after ale low t osc C15 2 t osc C40 ns (1) t avgv address valid to buswidth setup 2 t osc C75 ns t llgv ale low to buswidth setup t osc C60 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc C55 ns t rldv rd# active to input data valid t osc C22 ns t cldv clkout low to input data valid t osc C50 ns t rhdz end of rd# to input data float t osc ns t rxdx data hold after rd# inactive 0 ns the 87c196kr, jv, jt, jr, ca microcontroller meets these specifications. f xtal oscillator frequency 4 16 mhz (2) t osc oscillator period (1/f xtal ) 62.5 250 ns t xhch xtal1 high to clkout high or low 20 110 ns (3) t ofd clock failure to reset pulled low 4 40 s (7) t clcl clkout period 2 t osc ns t chcl clkout high period t osc C 10 t osc +15 ns t cllh clkout falling edge to ale rising C10 ca: C15 15 ca: 10 ns t llch ale/adv# falling edge to clkout rising C20 15 ns t lhlh ale/adv# cycle time 4 t osc ns t lhll ale/adv# high period t osc C 10 t osc +10 ns t avll address setup to ale/adv# falling edge t osc C 15 ns t llax address hold after ale/adv# falling edge t osc C 40 ns notes: 1. if max is exceeded, additional wait states will occur. 2. testing performed at 4 mhz; however, the device is static by design and will typically operate below 1 hz. 3. typical specifications, not guaranteed. 4. assuming back-to-back bus cycles. 5. 8-bit bus only. 6. t rlaz (max) = 5 ns by design. 7. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure.
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 19 t llrl ale/adv# falling edge to rd# falling edge t osc C 30 ns t rlcl rd# low to clkout falling edge 4 30 ns t rlrh rd# low period t osc C 5 ca: t osc C 10 ns t rhlh rd# rising edge to ale/adv# rising edge t osc t osc + 25 ns (4) t rlaz rd# low to address float 5 ns (6) t llwl ale/adv# falling edge to wr# falling edge t osc C 10 ns t clwl clkout low to wr# falling edge C5 25 ns t qvwh data stable to wr# rising edge t osc C 23 ns t chwh clkout high to wr# rising edge C10 15 ns t wlwh wr# low period t osc C 20 ns t whqx data hold after wr# rising edge t osc C 25 ns t whlh wr# rising edge to ale/adv# rising edge t osc C 10 t osc + 15 ns (4) t whbx bhe#, inst hold after wr# rising edge t osc C 10 ns t whax ad[15:8] hold after wr# rising edge t osc C 30 ns (5) t rhbx bhe#, inst hold after rd# rising edge t osc C 10 ns t rhax ad[15:8] hold after rd# rising edge t osc C 30 ns (5) table 6. ac characteristics (sheet 2 of 2) (over specified operating conditions); test conditions: capacitance load on all pins = 100 pf, rise and fall times = 10 ns, f osc =16mhz symbol parameter min max units notes: 1. if max is exceeded, additional wait states will occur. 2. testing performed at 4 mhz; however, the device is static by design and will typically operate below 1 hz. 3. typical specifications, not guaranteed. 4. assuming back-to-back bus cycles. 5. 8-bit bus only. 6. t rlaz (max) = 5 ns by design. 7. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure.
87c196kr, jv, jt, jr, ca microcontrollers automotive 20 datasheet figure 9. system bus timing a4649-01 xtal1 clkout ale rd# wr# bhe#, inst t osc t xhch t chcl t clcl t clch t llch t lhlh t lhll t llrl t rlrh t rhlh t rhdz t avll t llax t rldv address out data in t avdv t llwl t wlwh t whlh t qvwh t whqx data out address out address out valid address out t whax , t rhax t whbx , t rhbx t rlaz bus bus ad15:8
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 21 figure 10. ready/buswidth timing table 7. external clock drive symbol parameter min max units 1/t xlxl oscillator frequency 4 16 mhz t xlxl oscillator period (t osc ) 62.5 250 ns t xhxx high time 0.35 t osc 0.65 t osc ns t xlxx low time 0.35 t osc 0.65 t osc ns t xlxh rise time 10 ns t xhxl fall time 10 ns figure 11. external clock drive waveforms a4650-01 xtal1 clkout ale rd# ready t osc t xhch t chcl t clcl t cllh t llyx t avyv t avgv t llyv t llgv t clyx t clgx buswidth bus address out data a5842-01 t xlxx t xhxx t xhxl t xlxl 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v t xlxh 0.7 v cc + 0.5 v 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v
87c196kr, jv, jt, jr, ca microcontrollers automotive 22 datasheet figure 12. ac testing input, output waveforms figure 13. float waveforms table 8. thermal characteristics device and package q ja q jc an87c196kr (68-lead plcc) 41 c/w 14c/w an87c196jv, jt, jr (52-lead plcc) 42c/w 15c/w an87C196CA (68-lead plcc) 36.5c/w 10c/w notes: 1. q ja = thermal resistance between junction and the surrounding environment (ambient). measurements are taken 1 ft. away from case in air flow environment. q jc = thermal resistance between junction and package surface (case). 2. all values of q ja and q jc may fluctuate depending on the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. typical variations are 2c/w. 3. values listed are at a maximum power dissipation of 0.50 w. a4651-01 test points inputs outputs 2.0 v 0.8 v note: ac testing inputs are driven at 3.5 v for a logic 1 and 0.45 v for a logic 0 . timing measurements are made at 2.0 v for a logic 1 and 0.8 v for a logic 0. 3.5 v 0.45 v a5844-01 v load v load C 0.15 v v load + 0.15 v timing reference points v oh C 0.15 v v ol + 0.15 v note: for timing purposes, a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma.
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 23 4.4.1 explanation of ac symbols each symbol is two pairs of letters prefixed by t for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. 4.4.2 eprom specifications conditions signals hChigh aCaddress haChlda# lClow bCbhe# lCale/adv# vCvalid cCclkout rCrd# xCno longer valid dCdata wCwr#/wrh#/wri# zCfloating gCbuswidth xCxtal1 hChold# yCready table 9. ac eprom programming characteristics operating conditions: load capacitance = 150 pf; t c = 25c 5c; v ref = 5.0 v 0.5 v; v ss, angnd = 0 v; v pp =12.5v0.25v; ea#=12.5v0.25v; f osc =5.0mhz symbol parameter min max units t avll address setup time 0 t osc t llax address hold time 100 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t lllh pale# pulse width 50 t osc t plph prog# pulse width (3) 50 t osc t lhpl pale# high to prog# low 220 t osc t phll prog# high to next pale# low 220 t osc t phdx word dump hold time 50 t osc t phpl prog# high to next prog# low 220 t osc t pldv prog# low to word dump valid 50 t osc t shll reset# high to first pale# low 1100 t osc t phil prog# high to ainc# low 0 t osc t ilih ainc# pulse width 240 t osc t ilvh pver hold after ainc# low 50 t osc t ilpl ainc# low to prog# low 170 t osc t phvl prog# high to pver# valid 220 t osc notes: 1. run-time programming is done with f osc = 6.0 mhz to 10.0 mhz, v cc , v pd , v ref =5v0.5v, tc = 25c 5c and v pp = 12.5 v 0.25 v. for run-time programming over a full operating range, contact factory. 2. programming specifications are not tested, but guaranteed by design. 3. this specification is for the word dump mode. for programming pulses, use 300 t osc + 100 s.
87c196kr, jv, jt, jr, ca microcontrollers automotive 24 datasheet table 10. dc eprom programming characteristics symbol parameter min max units i pp v pp programming supply current 100 ca: 200 ma note: v pp must be within 1 v of v cc while v cc < 4.5 v. v pp must not have a low impedance path to ground or v ss while v cc > 4.5 v. figure 14. slave programming mode data program mode with single program pulse figure 15. slave programming mode in word dump or data verify mode with auto increment a5838-01 address/command t shll t phvl t llvh address/command data valid reset# ports 3/4 pale# p2.1 prog# p2.2 ainc# p2.0 t llax t lllh t lhpl t phdx t avll t dvpl t plph t phll a5839-01 ports 3/4 reset# address/command ver bits/wd dump t shll prog# p2.2 pale# p2.1 t pldv pver# p2.0 t ilpl addr addr + 2 t phdx t pldv t phdx ver bits/wd dump t phpl
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 25 4.4.3 a to d converter specifications the speed of the a/d converter in the 10-bit or 8-bit modes can be adjusted by setting the ad_time special function register to the appropriate value. the ad_time register only programs the speed at which the conversions are performed, not the speed at which it can convert correctly. the converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . v ref must not exceed v cc by more than 0.5 v since it supplies both the resistor ladder and the digital portion of the converter and input port pins. for testing purposes, after a conversion is started, the device is placed in the idle mode until the conversion is complete. testing is performed at v ref = 5.12 v and 16 mhz operating frequency. there is an ad_test register that allows for conversion on angnd and v ref as well as zero offset adjustment. the absolute error listed is without doing any adjustments. figure 16. slave programming mode timing in data program mode with repeated prog pulse and auto increment a5840-01 data p1 p2 t phpl t phil t ilpl t ilvh t ilih address/command data reset# ports 3/4 pale# p2.1 prog# p2.2 pver# p2.0 ainc# p2.4 valid for p2 valid for p1 table 11. a/d operating conditions (sheet 1 of 2) symbol description min max units t a automotive ambient temperature C40 +125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v notes: 1. angnd and v ss should nominally be at the same potential. 2. v ref must not exceed v cc by more than +0.5 v. 3. testing is performed at v ref = 5.12 v. 4. the value of ad_time must be selected to meet these specifications.
87c196kr, jv, jt, jr, ca microcontrollers automotive 26 datasheet t sam sample time 2.0 s t conv conversion time 16.5 ca: 15 19.5 ca: 18 s f osc oscillator frequency 4 16 mhz table 12. a/d operating parameter values parameter typical ( ?,1) min max units ?? resolution 1024 10 1024 10 level bits absolute error 0 C3 +3 lsbs full scale error 2 lsbs zero offset error 2 lsbs non-linearity 3 lsbs differential non-linearity > C0.5 +0.5 lsbs channel-to-channel matching 0 1 lsbs repeatability 0.25 0 lsbs ( 1 ) temperature coefficients: offset fullscale differential non-linearity 0.009 0.009 0.009 lsb/c ( 1 ) off isolation C60 db ( 1 )( 2 )( 3 ) feedthrough C60 db ( 1 )( 2 ) v cc power supply rejection C60 db ( 1 )( 2 ) input resistance 750 1.2 k w (1) dc input leakage 0 1 jt, jv = 2 ca = 3 a notes: ? these values are expected for most parts at 25c but are not tested or guaranteed. ?? an lsb, as used here, has a value of approximately 5 mv. (see automotive handbook for a/d glossary of terms.) 1. these values are not tested in production and are based on theoretical estimates and/or laboratory test. 2. dc to 100 khz. 3. multiplexer break-before-make guaranteed. table 11. a/d operating conditions (sheet 2 of 2) symbol description min max units notes: 1. angnd and v ss should nominally be at the same potential. 2. v ref must not exceed v cc by more than +0.5 v. 3. testing is performed at v ref = 5.12 v. 4. the value of ad_time must be selected to meet these specifications.
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 27 table 13. hold#/hlda# timings symbol description min max units notes t hvch hold setup 65 ns note 1 t clhal clkout low to hlda low C15 15 ns t clbrl clkout low to breq low C15 15 ns t azhal hlda# low to address float 25 ns t bzhal hlda# low to bhe#, inst, rd#, wr# weakly driven 25 ns t clhah clkout low to hlda high C15 15 ns t clbrh clkout low to breq high C15 15 ns t hahax hlda high to address valid C15 ns t hahbv hlda high to bhe, inst, rd, wr valid C10 ns t cllh clkout low to ale high C10 15 ns note: 1. to guarantee recognition at next clock. table 14. dc specifications in hold parameter min max units weak pullups on adv#, rd#, wr#, wrl#, bhe# 50 k 250 k v cc = 5.5 v, v in =0.45v weak pulldowns on ale, inst 10 k 50 k v cc = 5.5 v, v in =2.4v figure 17. hold timings a5883-01 clkout hold# hlda# breq# bus bhe#, inst, rd#, wr# ale t cllh t clhah t clbrh t hahax t hahbv t halbz t halaz t clbrl t clhal t hvch t hvch hold latency
87c196kr, jv, jt, jr, ca microcontrollers automotive 28 datasheet 4.4.4 ac characteristicsslave port figure 18. slave port waveform (slpl = 0) table 15. slave port timingC(slpl = 0) (see notes 1, 2, 3) symbol parameter min max units t savwl address valid to wr# low 50 ns t srhav rd# high to address valid 60 ns t srlrh rd# low period t osc ns t swlwh wr# low period t osc ns t srldv rd# low to output data valid 60 ns t sdvwh input data setup to wr# high 20 ns t swhqx wr# high to data invalid 30 ns t srhdz rd# high to data float 15 ns notes: 1. test conditions: f osc =16mhz, t osc = 60 ns, rise/fall time = 10 ns. capacitive pin load = 100 pf. 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. specifications above are advanced information and are subject to change. a5847-01 cs# ale / a1 rd# p3 wr# t swlwh t srldv t srhav t savwl t srlrh t sdvwh t swhqx t srhdz
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 29 figure 19. slave port waveform (slpl = 1) table 16. slave port timingC(slpl = 1) (see notes 1, 2, 3) symbol parameter min max units t selll cs# low to ale low 20 ns t srheh rd# or wr# high to cs# high 60 ns t sllrl ale low to rd# low t osc ns t srlrh rd# low period t osc ns t swlwh wr# low period t osc ns t savll address valid to ale low 20 ns t sllax ale low to address invalid 20 ns t srldv rd# low to output data valid 60 ns t sdvwh input data setup to wr# high 20 ns t swhqx wr# high to data invalid 30 ns t srhdz rd# high to data float 15 ns notes: 1. test conditions: f osc =16mhz, t osc = 60 ns, rise/fall time = 10 ns. capacitive pin load = 100 pf. 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. specifications above are advanced information and are subject to change. a5884-01 cs# ale rd# p3 wr# t swlwh t savll t srldv t srheh t selll t sllrl t srlrh t sdvwh t swhqx t srhdz t sllax
87c196kr, jv, jt, jr, ca microcontrollers automotive 30 datasheet 4.4.5 ac characteristicsserial port shift register mode 4.4.6 waveformserial portshift register mode 0 table 17. serial port timingshift register mode test conditions: t a = C40c to +125c; v cc = 5.0 v 10%; v ss = 0.0 v; load capacitance = 100 pf symbol parameter min max units t xlxl serial port clock period 8 t osc ns t xlxh serial port clock falling edge to rising edge 4 t osc C50 4 t osc + 50 ns t qvxh output data setup to clock rising edge 3 t osc ns t xhqx output data hold after clock rising edge 2 t osc C 50 ns t xhqv next output data valid after clock rising edge 2 t osc + 50 ns t dvxh input data setup to clock rising edge 2 t osc + 200 ns t xhdx (1) input data hold after clock rising edge 0 ns t xhqz (1) last clock rising to output float 5 t osc ns notes: 1. parameter not tested. figure 20. serial port waveformshift register mode a5841-01 valid valid valid valid valid valid valid valid rxd x (in) txd x 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh rxd x (out)
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 31 5.0 52-lead devices intel offers 52-lead versions of the 87c196kr device: the 87c196jv, jt, and jr devices. the first samples and production units use the 87c196kr die and bond it out in a 52-lead package. it is important to point out some functionality differences because of future devices or to remain software consistent with the 68-lead device. because of the absence of pins on the 52-lead device some functions are not supported. 52-lead unsupported functions: ? analog channels 0 and 1 ? inst pin functionality ? slpint pin support ? hld#/hlda# functionality ? external clocking/direction of timer1 ? wrh# or bhe functions ? dynamic buswidth ? dynamic wait state control the following is a list of recommended practices when using the 52-lead device: 1. external memory . use an 8-bit bus mode only. there is neither a wrh# or buswidth pin. the bus cannot dynamically switch from 8- to 16-bit or vice versa. set the ccb bytes to an 8-bit only mode, using wr# function only. 2. wait state control . use the ccb bytes to configure the maximum number of wait states. if the ready pin is selected to be a system function, the device will lockup waiting for ready. if the ready pin is configured as lsio (default after reset#), the internal logic will receive a logic 0 level and insert the ccb defined number of wait states in the bus cycle. don't use irc = 111. 3. nmi support . the nmi is not bonded out. make the nmi vector at location 203eh vector to a return instruction. this is for glitch safety protection only. 4. auto-programming mode . the 52-lead device will only support the 16-bit zero wait state bus during auto-programming. 5. epa4 through epa7 . since the jr, jt, and jv devices use the kr silicon, these functions are in the device, just not bonded out. a programmer can use these as compare only channels or for other functions like software timer, start an a/d conversion, or reset timers. 6. slave port support . the slave port cannot be easily used on 52-lead devices due to 5.4/ slpint and p5.1/slpcs not being bonded-out.
87c196kr, jv, jt, jr, ca microcontrollers automotive 32 datasheet 7. port functions . some port pins have been removed. p5.7, p5.6, p5.5, p5.1, p6.2, p6.3, p1.4 through p1.7, p2.3, p2.5, p0.0 and p0.1. the pxreg, pxssel, and pxio registers can still be updated and read. the programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software. treat these bits as reserved. additionally, these port pins should be setup internally by software as follows: a. written to pxreg as 1 or 0. b. configured as push/pull, pxio as 0. c. configured as lsio. warning: this configuration will effectively strap the pin either high or low. do not configure as open drain output 1, or as an input pin. this device is cmos. 6.0 design considerations 6.1 87c196kr, jv, jt, jr, and ca design considerations 1. epa timer reset/write conflict if the user writes to the epa timer at the same time that the timer is reset, it is indeterminate which will take precedence. users should not write to a timer if using epa signals to reset it. 2. valid time matches the timer must increment/decrement to the compare value for a match to occur. a match does not occur if the timer is loaded with a value equal to an epa compare value. matches also do not occur if a timer is reset and 0 is the epa compare value. 3. p6 pin.4-.7 not updated immediately values written to p6 reg are temporarily held in a buffer. if p6 mode is cleared, the buffer is loaded into p6 reg.x. if p6 mode is set, the value stays in the buffer and is loaded into p6 reg.x when p6 mode.x is cleared. since reading p6 reg returns the current value in p6. reg and not the buffer, changes to p6 reg cannot be read until/unless p6 mode.x is cleared. 4. write cycle during reset if reset occurs during a write cycle, the contents of the external memory device may be corrupted. 5. indirect shift instruction the upper 3 bits of the byte register holding the shift count are not masked completely. if the shift count register has the value 32 x n , where n = 1, 3, 5, or 7, the operand will be shifted 32 times. this should have resulted in no shift taking place. 6. p2.7 (clkout) p2.7 (clkout) does not operate in open drain mode. 7. clkout the clkout signal is active on p2.7 during reset for the kr, jv, jt, jr and ca devices.
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 33 8. epa overruns epa lock-up can occur if overruns are not handled correctly, refer to intel techbit #db0459 understanding epa capture overruns, dated 12-9-93. applies to epa channels with interrupts and overruns enabled (on/rt bit in epa_control register set to 1). 9. indirect addressing with auto-increment for the special case of a pointer pointing to itself using auto-increment, an incorrect access of the incremented pointer address will occur instead of an access to the original pointer address. all other indirect auto-increment accesses will note be affected. please refer to techbit #mc0593. incorrect sequence: correct sequence: 10. jv additional register ram the 8xc196jv has a total of 1.5 kbytes of register ram. the ram is located in two memory ranges: 0000h C 03ffh and 1c00h C 1dffh. 6.2 87c196jr c-step to jr d-step C or C jv/jt a-step design considerations this section documents differences between the 87c197jv a-step (jv-a)/87c196jt a-step (jt- a)/87c196jr d-step (jr-d) and the 87c196jr c-step/(jr-c). for a list of design considerations between 68-lead and 52-lead devices, please refer to the 52-lead device design considerations section of this datasheet. since the 87c196jv and jt are simply memory scalars of the 87c196jr, the term ``jr'' in this section will refer to jv, jt, and jr versions of the device unless otherwise noted. the jr-c is simply a 87c196kr c-step (kr-c) device packaged within a 52-lead package. this reduction in pin count necessitated not bonding-out certain pins of the kr-c device. the fact that these removed pins were still present on the device but not available to the outside world allowed the programmer to take advantage of some of the 68-lead kr features. the jr-d is a fully-optimized 52-lead device based on the 87c196kr c-step device. the kr-c design data base was used to assure that the jr-d would be fully compatible with the kr-c, jr-c and other kx family members. the main differences between the jr-d and the jr-c is that several of the unused (not bonded-out) functions on the jr-c were removed altogether on the jr-d. following is a list of differences between the jr-c and the jr-d: 1. port3 push-pull operation it was discovered on jr-c that if port3 is selected for push-pull operation (p34_drv register) during low speed i/o (lsio), the port was driving data when the system bus was attempting to input data. it is rather unlikely that this errata would affect an application because the application would have to use port3 for both lsio and as an external addr/data bus. nonetheless, this errata was corrected on the jr-d. ld ax,#ax ; results in ax being incremented by 1 and the contents of the address pointed to by ax+1 to be loaded into bx. ldb bx,[ax]+ ; ld ax,#bx ; where ax 1 bx. results in the contents of the address pointed to by ax to be loaded into bx and ax incremented by 1. ldb cx,[ax]+ ;
87c196kr, jv, jt, jr, ca microcontrollers automotive 34 datasheet 2. v oh2 strengthened the dc characteristics section of the automotive kr datasheet contains a parameter, v oh2 (output high voltage in reset (bd ports)), which is specified at v cc C1v min at i oh2 = C15 a. this specification indicates the strength of the internal weak pull-ups that are active during and after reset. these weak pull-ups stay active until the user writes to pxmode (previously known as pxssel) and configures the port pin as desired. these pull-ups do not meet this v oh2 spec on the jr-c. the weak pull-ups on specified jr-d ports have been enhanced to meet the published specification of i oh2 =C15 a. 3. once mode once mode is entered by holding a single pin low on the rising edge of reset#. on the kr, this pin is p5.4/slpint. the jr-c does not support once mode since p5.4/slpint (once mode entry pin) is not bonded-out on these devices. to provide once mode on the jr-d, the once mode entry function was moved from p5.4/slpint to p2.6/hlda. this will allow the jr-d to enter once mode using p2.6 instead of removed pin p5.4. 4. port0 on the jr-c, p0.0 and p0.1 are not bonded out. however, these inputs are present in the device and reading them will provide an indeterminate result. on the jr-d, the analog inputs for these two channels at the multiplexer are tied to v ref . therefore, initiating an analog conversion on ach0 or ach1 will result in a value equal to full scale (3ffh). on the jr-d, the digital inputs for these two channels are tied to ground, therefore reading p0.0 or p0.1 will result in a digital ``0''. 5. port1 on the jr-c, p1.4, p1.5, p1.6 and p1.7 are not bonded out but are present internally on the device. this allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. however, to maintain compatibility with d-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. these bits should be treated as reserved. on the jr-d, unused port logic for these four port pins has been removed from the device and is not available to the programmer. corresponding bits in the port registers have been ``hard- wired'' to provide the following results when read: 6. port2 on the jr-c, p2.3 and p2.5 are not bonded out but are present internally on the device. this allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. however, to maintain compatibility with d-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. these bits should be treated as reserved. on the jr-d, unused port logic for these two port pins has been removed from the device and is not available to the programmer. corresponding bits in the port registers have been hardwired to provide the following results when read: register bits when read p1_pin.x (x = 4,5,6,7) 1 p1_reg.x (x = 4,5,6,7) 1 p1_dir.x (x = 4,5,6,7) 1 p1_mode.x (x = 4,5,6,7) 0 note: writing to these bits will have no effect.
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 35 7. port5 on the jr-c, p5.1, p5.4, p5.5, p5.6 and p5.7 are not bonded out but are present internally on the device. this allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. however, to maintain compatibility with d-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. these bits should be treated as reserved. on the jr-d, unused port logic for these five port pins has been removed from the device and is not available to the programmer. corresponding bits in the port registers have been hardwired to provide the following results when read: 8. port6 on the jr-c, p6.2 and p6.3 are not bonded out but are present internally on the device. this allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. however, to maintain compatibility with d-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. these bits should be treated as reserved. on the jr-d, unused port logic for these two port pins has been removed from the device and is not available to the programmer. corresponding bits in the port registers have been hardwired to provide the following results when read: register bits when read p2_pin.x (x = 3,5) 1 p2_reg.x (x = 3,5) 1 p2_dir.x (x = 3,5) 1 p2_mode.x (x = 3,5) 0 note: writing to these bits will have no effect. register bits when read p5_pin.x (x = 1,4,5,6,7) 1 p5_reg.x (x = 1,4,5,6,7) 1 p5_dir.x (x = 1,4,5,6,7) 1 p5_mode.x (x = 1,4,6) 0 p5_mode.x (x = 5)(ea# = 0) 1 p5_mode.x (x = 5)(ea# = 1) 0 p5_mode.x (x = 7) 1 note: writing to these bits will have no effect. register bits when read p6_pin.x (x = 2,3) 1 p6_reg.x (x = 2,3) 1 p6_dir.x (x = 2,3) 1 p6_mode.x (x = 2,3) 0 note: writing to these bits will have no effect.
87c196kr, jv, jt, jr, ca microcontrollers automotive 36 datasheet 9. epa channels 4 through 7 the jr c-step device is simply a 68-lead kr-c device packaged in a 52-lead package. the reduced pin-out is achieved by not bonding-out the unsupported pins. epa4Cepa7 are among these pins that are not bonded-out. the fact that epa4Cepa7 are still present allows the programmer to use these channels as software timers, to start a/d conversions, reset timers, etc. all of the port pin logic is still present and it is possible to use the epa to toggle these pins internally. please refer to the 52-lead device section in this datasheet for further information. on the jr d-step, the epa4Cepa7 logic has not been removed from the device. this allows the programmer to still use these channels (as on the c-step) for software timers, etc. the only difference is that the associated port pin logic has been removed and does not exist internally. to maintain c-step to d-step compatibility, programmers should make sure that their software does not rely upon the removed pins. 6.2.1 87C196CA design considerations the 87C196CA device is a memory scalar of the 87c196kr device with integrated can 2.0. the ca is designed for strict functional and electrical compatibility to the kx family as well as integration of on-chip networking capability. the 87C196CA has fewer peripheral functions than the 196kr, due in part to the integration of the can peripheral. following are the functionality differences between the 196kr and 196ca devices. 196kr features unsupported on the 196ca: 1. external memory removal of the buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus mode or vice versa. the programmer must define the bus mode by setting the associated bits in the ccb. 2. auto-programming mode the 87C196CA device will only support the 16-bit zero wait state bus during auto- programming. 3. epa4 through epa7 since the ca device is based on the kr design, these functions are in the device, however there are no associated pins. a programmer can use these as compare only channels or for other functions like software timer, start an a/d conversion, or reset timers. 4. slave port support the slave port can not be used on the 196ca due to a function change for p5.4/slpint and p5.1/slpcs not being bonded-out. 5. port functions some port pins have been removed. p5.1, p6.2, p6.3, p1.4 through p1.7, p2.3, p2.5, p0.0 and p0.1. the pxreg, pxssel, and pxio registers can still be updated and read. the programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software. treat these bits as reserved. additionally, these port pins should be setup internally by software as follows: ? analog channels 0 and 1 ? inst pin functionality ? slpint and slpcs pin support ? hld/hlda functionality ? external clocking/direction of timer1 ? quadrature clocking timer 1 ? dynamic buswidth ? epa capture channels 4C7
automotive 87c196kr, jv, jt, jr, ca microcontrollers datasheet 37 a . w r i t t e n t o p x r e g a s ` ` 1 '' o r ` ` 0 ''. b. configured as push/pull, pxio as ``0''. c. configured as lsio. this configuration will effectively strap the pin either high or low. do not configure as open drain output `'1'', or as an input pin. this device is cmos. 6. epa timer reset/write conflict if the user writes to the epa timer at the same time that the timer is reset, it is indeterminate which will take precedence. users should not write to a timer if using epa signals to reset it. 7. valid time matches the timer must increase/decrease to the compare value for a match to occur. a match does not occur if the timer is loaded with a value equal to an epa compare value. matches also do not occur if a timer is reset and 0 is the epa compare value. 8. write cycle during reset if reset occurs during a write cycle, the contents of the external memory device may be corrupted. 9. indirect shift instruction the upper 3 bits of the byte register holding the shift count are not masked completely. if the shift count register has the value 32 c n, where n e 1, 3, 5, or 7, the operand will be shifted 32 times. this should have resulted in no shift taking place. 10. p2.7 (clkout) p2.7 (clkout) does not operate in open drain mode. 7.0 revision history revision date description 007 05/98 removed the 87c196kq and 87c196jq products and related information from datasheet. added 87C196CA product and related information to datasheet. 006 11/95 the 87c196jv datasheet status has been moved from product preview to that of no marking. a by design note was added to the t rlaz specification. in the design considerations section, the #7.clkout design consideration was corrected. only the two most current revision histories of this datasheet were retained in the datasheet revision history section.

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